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ST24C04, st25c04 st24w04, st25w04 4 kbit serial i 2 c bus eeprom with user-defined block write protection not for new design december 2002 1/16 this is information on a product still in production but not recommended for new designs. ai00851e 2 e1-e2 sda v cc st24x04 st25x04 mode/wc* scl v ss pre figure 1. logic diagram 1 million erase/write cycles with 40 years data retention single supply voltage: C 3v to 5.5v for st24x04 versions C 2.5v to 5.5v for st25x04 versions hardware write control versions: st24w04 and st25w04 programmable write protection two wire serial interface, fully i 2 c bus compatible byte and multibyte write (up to 4 bytes) page write (up to 8 bytes) byte, random and sequential read modes self timed programming cycle automatic address incrementing enhanced esd/latch up performances description this specification covers a range of 4 kbits i 2 c bus eeprom products, the st24/25c04 and the st24/25w04. in the text, products are referred to as st24/25x04, where "x" is: "c" for standard version and "w" for hardware write control ver- sion. pre write protect enable e1-e2 chip enable inputs sda serial data address input/output scl serial clock mode multibyte/page write mode (c version) wc write control (w version) v cc supply voltage v ss ground table 1. signal names 8 1 so8 (m) 150mil width 8 1 psdip8 (b) 0.25mm frame note: wc signal is only available for st24/25w04 products.
the st24/25x04 are 4 kbit electrically erasable programmable memories (eeprom), organized as 2 blocks of 256 x8 bits. they are manufactured in stmicroelectronicss hi-endurance advanced cmos technology which guarantees an endur- ance of one million erase/write cycles with a data retention of 40 years. both plastic dual-in-line and plastic small outline packages are available. the memories are compatible with the i 2 c stand- ard, two wire serial interface which uses a bi-direc - tional data bus and serial clock. the memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the i 2 c bus defini- tion. this is used together with 2 chip enable inputs (e2, e1) so that up to 4 x 4k devices may be attached to the i 2 c bus and selected individually. the memories behave as a slave device in the i 2 c protocol with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition generated by the bus master. the start condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit. sda v ss scl mode/wc e1 pre v cc e2 ai00852e st24x04 st25x04 1 2 3 4 8 7 6 5 figure 2a. dip pin connections 1 ai01107e 2 3 4 8 7 6 5 sda v ss scl mode/wc e1 pre v cc e2 st24x04 st25x04 figure 2b. so pin connections description (contd) symbol parameter value unit t a ambient operating temperature C40 to 125 c t stg storage temperature C65 to 150 c t lead lead temperature, soldering (so8 package) (psdip8 package) 40 sec 10 sec 215 260 c v io input or output voltages C0.6 to 6.5 v v cc supply voltage C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (2) 4000 v electrostatic discharge voltage (machine model) (3) 500 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not i mplied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and oth er relevant quality documents. 2. mil-std-883c, 3015.7 (100pf, 1500 ). 3. eiaj ic-121 (condition c) ( 200pf, 0 ). table 2. absolute maximum ratings (1) 2/16 st24/25c04, st24/25w04
mode r w bit mode bytes initial sequence current address read 1 x 1 start, device select, r w = 1 random address read 0 x1 start, device select, r w = 0, address, 1 restart, device select, r w = 1 sequential read 1 x 1 to 512 similar to current or random mode byte write 0 x 1 start, device select, r w = 0 multibyte write (2) 0 v ih 4 start, device select, r w = 0 page write 0 v il 8 start, device select, r w = 0 notes: 1. x = v ih or v il 2. multibyte write not available in st24/25w04 versions. table 4. operating modes (1) device code chip enable block select r w bit b7 b6 b5 b4 b3 b2 b1 b0 device select 1 0 1 0 e2 e1 a8 r w note: the msb b7 is sent first. table 3. device select code when writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. when data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. data transfers are termi- nated with a stop condition. power on reset: v cc lock out write protect. in order to prevent data corruption and inadvertent write operations during power up, a power on reset (por) circuit is implemented. until the v cc voltage has reached the por threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. in the same way, when v cc drops down from the operating voltage to below the por threshold value, all operations are disabled and the device will not respond to any command. a stable v cc must be applied before applying any logic signal. signal descriptions serial clock (scl). the scl input pin is used to synchronize all data in and out of the memory. a resistor can be connected from the scl line to v cc to act as a pull up (see figure 3). serial data (sda). the sda pin is bi-directional and is used to transfer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a resistor must be connected from the sda bus line to v cc to act as pull up (see figure 3). chip enable (e1 - e2). these chip enable inputs are used to set the 2 least significant bits (b2, b3) of the 7 bit device select code. these inputs may be driven dynamically or tied to v cc or v ss to establish the device select c ode. protect enable (pre). the pre input pin, in ad- dition to the status of the block address pointer bit (b2, location 1ffh as in figure 7), sets the pre write protection active. mode (mode). the mode input is available on pin 7 (see also wc feature) and may be driven dynami- cally. it must be at v il or v ih for the byte write mode, v ih for multibyte write m ode or v il for page write mode. when unconnected, the mode i nput is internally read as v ih (multibyte write mode). write control ( wc). an hardware write control feature ( wc) is offered only for st24w04 and st25w04 versions on pin 7. this feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. the write control sig- nal is used to enable ( wc = v ih ) or disable ( wc = v il ) the internal write protection. when uncon- nected, the wc input is internally read as v il and the memory area is not write protected. 3/16 st24/25c04, st24/25w04
ai01100 v cc c bus sda r l master r l scl c bus 100 200 300 400 0 4 8 12 16 20 c bus (pf) r l max (k ) v cc = 5v figure 3. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus the devices with this write control feature no longer support the multibyte write mode of opera- tion, however all other write modes are fully sup- ported. refer to the an404 application note for more de- tailed information about write control feature. device operation i 2 c bus backgr ound the st24/25x04 support the i 2 c protocol. this protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master will always initiate a data transfer and will provide the serial clock for syn- chronisation. the st24/25x04 are always slave devices in all communications. start condition. start is identified by a high to low transition of the sda line while the clock scl is stable in the high state. a start condition must precede any command for data transfer. except during a programming cycle, the st24/25x04 con- tinuously monitor the sda and scl signals for a start condition and will not respond unless one is given. stop condition. stop is identified by a low to high transition of the sda line while the clock scl is stable in the high state. a stop condition termi- nates communication between the st24/25x04 and the bus master. a stop condition at the end of a read command, after and only after a no acknowledge, forces the standby state. a stop condition at the end of a write command triggers the internal eeprom write cycle. acknowledge bit (ack). an acknowl edge s ignal is used to indicate a successfull data transfer. the bus transmitter, either master or slave, will release the sda bus after sending 8 bits of data. during the 9th clock pulse period the receiver pulls the sda bus low to acknowl edge the receipt of the 8 bits of data. data input. during data input the st24/25x04 sample the sda bus signal on the rising edge of the clock scl. note that for correct device opera- tion the sda signal must be stable during the clock low to high transition and the data must change only when the scl line is low. memory addressing. to start communication be- tween the bus master and the slave st24/25x04, the master must initiate a start condition. follow- ing this, the master sends onto the sda bus line 8 bits (msb first) corresponding to the dev ice select code (7 bits) and a read or write bit. signal descriptions (contd) 4/16 st24/25c04, st24/25w04
symbol parameter test condition min max unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance (st24/25w04) v in 0.3 v cc 520k z wch wc input impedance (st24/25w04) v in 0.7 v cc 500 k t lp low-pass filter input time constant (sda and scl) 100 ns note: 1. sampled only, not 100% tested. table 5. input parameters (1) (t a = 25 c, f = 100 khz ) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 2 a i lo output leakage current 0v v out v cc sda in hi-z 2 a i cc supply current (st24 series) v cc = 5v, f c = 100khz (rise/fall time < 10ns) 2ma supply current (st25 series) v cc = 2.5v, f c = 100khz 1 ma i cc1 supply current (standby) (st24 series) v in = v ss or v cc , v cc = 5v 100 a v in = v ss or v cc , v cc = 5v, f c = 100khz 300 a i cc2 supply current (standby) (st25 series) v in = v ss or v cc , v cc = 2.5v 5 a v in = v ss or v cc , v cc = 2.5v, f c = 100khz 50 a v il input low voltage (scl, sda) C0.3 0.3 v cc v v ih input high voltage (scl, sda) 0.7 v cc v cc + 1 v v il input low voltage (e1-e2, pre, mode, wc) C0.3 0.5 v v ih input high voltage (e1-e2, pre, mode, wc) v cc C 0.5 v cc + 1 v v ol output low voltage (st24 series) i ol = 3ma, v cc = 5v 0.4 v output low voltage (st25 series) i ol = 2.1ma, v cc = 2.5v 0.4 v table 6. dc characteristics (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v cc = 3v to 5.5v or 2.5v to 5.5v) 5/16 st24/25c04, st24/25w04
the 4 most significant bits of the device select code are the device type i dentifier, corresponding to the i 2 c bus definition. for these memories the 4 bits are fixed as 1010b. the following 2 bits identify the specific memory on the bus. they are matched to the chip enable signals e2, e1. thus up to 4 x 4k memories can be connected on the same bus giving a memory capacity total of 16 kbits. after a start condition any memory on the bus will iden- tify the device code and compare the following 2 bits to its chip enable inputs e2, e1. the 7th bit sent is the block number (one block = 256 bytes). the 8th bit sent is the read or write bit (r w), this bit is set to 1 for read and 0 for write operations. if a match is found, the corresponding memory will acknowledge the identification on the sda bus during the 9th bit time. input rise and fall times 50ns input pulse voltages 0.2v cc to 0.8v cc input and output timing ref. voltages 0.3v cc to 0.7v cc ac measurement conditions ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc figure 4. ac testing input output waveforms device operation (contd) symbol alt parameter min max unit t ch1ch2 t r clock rise time 1 s t cl1cl2 t f clock fall time 300 ns t dh1dh2 t r input rise time 1 s t dl1dl1 t f input fall time 300 ns t chdx (1) t su:sta clock high to input transition 4.7 s t chcl t high clock pulse width high 4 s t dlcl t hd:sta input low to clock low (start) 4 s t cldx t hd:dat clock low to input transition 0 s t clch t low clock pulse width low 4.7 s t dxcx t su:dat input transition to clock transition 250 ns t chdh t su:sto clock high to input high (stop) 4.7 s t dhdl t buf input high to input low (bus free) 4.7 s t clqv (2) t aa clock low to next data out valid 0.3 3.5 s t clqx t dh data out hold time 300 ns f c f scl clock frequency 100 khz t w (3) t wr write time 10 ms notes: 1. for a restart condition, or following a write cycle. 2. the minimum value delays the falling/rising edge of sda away from scl = 1 in or der to avoid unwanted start and/or stop conditions. 3. in the multibyte write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 addr ess msb are not constant) the maximum programming time is doubled to 20ms. table 7. ac characteristics (t a = 0 to 70 c, C20 to 85 c or C40 to 85 c; v cc = 3v to 5.5v or 2.5v to 5.5v) 6/16 st24/25c04, st24/25w04
scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop & bus free data valid tclqv tclqx data output tchdh stop condition tchdx start condition write cycle tw ai00795b figure 5. ac waveforms write operations the multibyte write mode (only available on the st24/25c04 versions) is selected when the mode pin is at v ih and the page write mode when mode pin is at v il . the mode pin may be driven dynami- cally with cmos input levels. following a start condition the master sends a device select code with the r w bit reset to 0. the memory acknowledges this and waits for a byte address. the byte address of 8 bits provides ac- cess to one block of 256 bytes of the memory. after receipt of the byte address the device again re- sponds with an acknowledge. for the st24/25w04 versions, any write command with wc = 1 will not modify the memory content. byte write. in the byte write mode the master sends one data byte, which is acknowledged by the memory. the master then terminates the transfer by generating a stop condition. the write mode is independant of the state of the mode pin which could be left floating if only this mode was to be used. however it is not a recommended operating mode, as this pin has to be connected to either v ih or v il , to minimize the stand-by current. 7/16 st24/25c04, st24/25w04
scl sda scl sda sda start condition sda input sda change ai00792 stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition figure 6. i 2 c bus protocol multibyte write. for the multibyte write mode, the mode pin must be at v ih . the multibyte write mode can be started from any address in the memory. the master sends from one up to 4 bytes of data, which are each acknowledged by the mem- ory. the transfer is terminated by the master gen - erating a stop condition. the duration of the write cycle is t w = 10ms maximum except when bytes are accessed on 2 rows (that is have different values for the 6 most significant address bits a7- a2), the programming time is then doubled to a maximum of 20ms. writing more than 4 bytes in the multibyte write mode may modify data bytes in an adjacent row (one row is 8 bytes long). however, the multibyte write can properly write up to 8 consecutive bytes as soon as the first address of these 8 bytes is the first address of the row, the 7 following bytes being written in the 7 following bytes of this same row. page write. for the page write mode, the mode pin must be at v il . the page write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is the 5 most significant mem- 8/16 st24/25c04, st24/25w04
ory address bits (a7-a3) are the same inside one block. the master sends from one up to 8 bytes of data, which are each acknowledged by the mem- ory. after each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. the transfer is terminated by the master generating a stop condition. care must be taken to avoid address counter roll-over which could result in data being overwritten. note that, for any write mode, the generation by the master of the stop condition starts the internal memory pro- gram cycle. all inputs are disabled until the comple- tion of this cycle and the memory will not respond to any request. minimizing system delays by polling on ack. during the internal write cycle, the memory discon- nects itself from the bus in order to copy the data from the internal latches to the memory cells. the maximum value of the write time (t w ) is given in the ac characteristics table, since the typical time is shorter, the time seen by the system may be re- duced by an ack polling sequence issued by the master. write cycle in progress ai01099b next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop proceed write operation proceed random address read operation send byte address first byte of instruction with rw = 0 already decoded by st24xxx figure 8. write cycle polling using ack ai00855b 1ffh b7 b3 b2 xx 100h block 1 block 0 protect flag enable = 0 disable = 1 8 byte boundary address protect location figure 7. memory protection 9/16 st24/25c04, st24/25w04
the sequence is as follows: C initial condition: a write is in progress (see figure 8). C step 1: the master issues a start condition followed by a device select byte (1st byte of the new instruction). C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the master goes back to step 1. if the memory has terminated the internal write cycle, it will re- spond with an ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during step 1). write protection. data in the upper block of 256 bytes of the memory may be write protected. the memory is write protected between a boundary address and the top of memory (address 1ffh) when the pre input pin is taken high and when the protect flag (bit b2 in location 1ffh) is set to 0. the boundary address is user defi ned by wr iting it in the block address pointer. the block address pointer is an 8 bit eeprom register located at the address 1ffh. it is composed by 5 msbs address pointer, which defines the bottom boundary ad- dress, and 3 lsbs which must be programmed at device operation (contd) 0. this address pointer can therefore address a boundary in steps of 8 bytes. the sequence to use the write protected feature is: C write the data to be protected into the top of the memory, up to, but not including, location 1ffh; C set the protection by writing the correct bottom boundary address in the address pointer (5 msbs of location 1ffh) with bit b2 (protect flag) set to 0. note that for a correct foncti onality of the memory, all the 3 lsbs of the block address pointer must also be programmed at 0. the area will now be protected when the pre input pin is taken high. while the pre input pin is read at 0 by the memory, the location 1ffh can be used as a normal eeprom byte. caution: special attention must be used when using the protect mode together with the multibyte write mode (mode input pin high). if the multibyte write starts at the location right below the first byte of the write protected area, then the instruction will write over the first 3 bytes of the write protected area. the area protected is therefore smaller than the content defined in the location 1ffh, by 3 bytes. this does not apply to the page write mode as the address counter roll-over and thus cannot go above the 8 bytes lower boundary of the protected area. stop start byte write dev sel byte addr data in start multibyte and page write dev sel byte addr data in 1 data in 2 ai00793 stop data in n ack ack ack r/w ack ack ack r/w ack ack figure 9. write modes sequence (st24/25c04) 10/16 st24/25c04, st24/25w04
stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 wc data in 2 ai01101b page write (cont'd) wc (cont'd) stop data in n ack ack ack r/w ack ack ack r/w ack ack figure 10. write modes se quence with write control = 1 (st24/25w04) read operations read operations are independent of the state of the mode pin. on delivery, the memory content is set at all "1s" (or ffh). current address read. the memory has an inter- nal byte address counter. each time a byte is r ead, this counter is incremented. for the current ad- dress read mode, following a start condition, the master sends a memory address with the r w bit set to 1. the memory acknowledges this and outputs the byte addressed by the internal byte address counter. this counter is then incremented. the master does not acknowledge the byte out- put, but terminates the transfer with a stop con- dition. random address read. a dummy write is per- formed to load the address into the address counter, see figure 11. this is followed by another start condition from the master and the byte address is repeated with the r w bit set to 1. the memory acknowledges this and outputs the byte addressed. the master have to not acknowledge the byte output, but terminates the transfer with a stop condition. sequential read. this mode can be initiated with either a current address read or a random ad- dress read. however, in this case the master does acknowledge the data byte output and the memory continues to output the next byte in se- quence. to terminate the stream of bytes, the master must not acknowledge the last byte out- 11/16 st24/25c04, st24/25w04
put, but must generate a stop condition. the output data is from consecutive byte addresses, with the internal byte address counter automat- ically incremented after each byte output. after a count of the last memory address, the address counter will roll- over and the memory will continue to output data. acknowledge in read mode. in all read modes the st24/25x04 wait for an acknowledge during the 9th bit time. if the master does not pull the sda line low during this time, the st24/25x04 terminate the data transfer and switches to a standby state. start dev sel * byte addr start dev sel data out 1 ai00794c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack figure 11. read modes sequence note: * the 7 most significant bits of dev sel bytes of a random read (1st byte and 3rd byte) must be identical. device operation (contd) 12/16 st24/25c04, st24/25w04
ordering information scheme notes: 3 * temperature range on special request only. parts are shipped with the memory content set at all "1s" (ffh). for a list of available options (operating voltage, range, package, etc...) or for furt her informat ion on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. operating voltage ST24C04 3v to 5.5v st24w04 3v to 5.5v st25c04 2.5v to 5.5v st25w04 2.5v to 5.5v range standard hardware write control standard hardware write control package b psdip8 0.25mm frame m so8 150mil width temperature range 1 0 to 70 c 5 C20 to 85 c 6 C40 to 85 c 3 * C40 to 125 c option tr tape & reel packing example: ST24C04 m 1 tr 13/16 st24/25c04, st24/25w04
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 3.90 5.90 0.154 0.232 a1 0.49 C 0.019 C a2 3.30 5.30 0.130 0.209 b 0.36 0.56 0.014 0.022 b1 1.15 1.65 0.045 0.065 c 0.20 0.36 0.008 0.014 d 9.20 9.90 0.362 0.390 e 7.62 C C 0.300 C C e1 6.00 6.70 0.236 0.264 e1 2.54 C C 0.100 C C ea 7.80 C 0.307 C eb C 10.00 C 0.394 l 3.00 3.80 0.118 0.150 n8 8 drawing is not to scale psdip8 - 8 pin plastic skinny dip, 0.25mm lead frame 14/16 st24/25c04, st24/25w04
so-a e n cp b e a d c l a1 1 h h x 45? symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 drawing is not to scale so8 - 8 lead plastic small outline, 150 mils body width 15/16 st24/25c04, st24/25w04
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved all other names are the property of their respective owners stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united stat es www.st.com 16/16 st24/25c04, st24/25w04

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